COMMENT ⊗   VALID 00007 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002	PDP-11 ARM INTERFACE by Tom Gafford, description by Bo Eross
C00005 00003	774000, DAC SAMPLE, STATUS/CONTROL:
C00008 00004	774002, TACHOMETER AND BRAKE REGISTER:
C00010 00005	774004, ADC STATUS/CONTROL:
C00015 00006	DAC AND ADC CHANNEL ASSIGNMENTS:
C00016 00007	ARM INTERFACE PROGRAMMING NOTES
C00019 ENDMK
C⊗;
PDP-11 ARM INTERFACE by Tom Gafford, description by Bo Eross

The arm interface is a multi-channel analog-to-digital-to-analog
converter system with some special-purpose logic designed to make
it convenient to operate a mechanical device such as a Scheinman
arm.  From the programming point of view, the interface consists
of four registers on the Unibus and three interrupt vectors.
Briefly, the registers are

UNIBUS
ADDRESS		DESCRIPTION

774000	DAC data, status and control.  Contains a four-bit channel
	address, an eight-bit data sample, and four control bits.
	The DAC is used to output the driving force values to the
	motors and the zero-point settings to the sensor A to D
	converter.

774002	Tachometer and brake register.  Holds control bits that
	engage and disengage the brakes on the arm joints (and
	also disable and enable the corresponding motors), and
	enable or disable direct tachometer feedback to the motor
	drivers.

774004	ADC control and status.  Contains a six-bit ADC channel select
	and five control bits.  The ADC is used for reading sensors
	such as joint position potentiometers, tachometers, and
	finger touch contacts.

774006	ADC sample.  This contains the data from the selected ADC
	channel as a signed integer.


The interrupt vectors are

130	DAC output done.
134	ADC conversion done.
200	Alarm condition.

All three interrupts are at priority BR7.

In the detailed description that follows, the abbrevation "R" stands for
bits that may be read but not written (reflecting the internal state of
the interface), "RW" for bits that may be both read and written (data and
mode bits), and "PW" for bits that may be written but not read (control
bits that cause an action, read back as zeros).
774000, DAC SAMPLE, STATUS/CONTROL:

__15___14___13___12___11___10____9____8____7____6____5____4____3____2____1____0__
|                                       |DONE|INT |ALT |ERR | CHANNEL ADDRESS   |
| MSB      DAC SAMPLE               LSB |    |ENBL|    |RSET|                   |
|__________________RW___________________|_R__|_RW_|_RW_|_PW_|________RW_________|

CHANNEL ADDRESS tells which of the DAC output channels the sample is for.

DAC SAMPLE is a signed 8-bit integer that the selected channel is to convert to
an output voltage.

DONE comes on when the DAC has finished converting the last sample.  It goes off
whenever you write into the sample byte.

INT ENBL, if on, enables the interface to cause a priority 7 interrupt through
location 130 when DONE is on.

ALT is a random control bit which can be used to cause side effects in any device
associated with the DAC. Its particular use in the original design is to zero the
force sensor multiplexor counter when the channel which supplies the zero set
voltage is selected.

ERR RESET: writing a one into this bit clears the alarm conditions.

If you only write the low byte of this register, you merely set the mode, and
select an output channel.  No actual output happens.  Writing into just the high
byte causes an output conversion to start on the selected channel.  Writing the
full register first selects the channel, then outputs the sample. 
774002, TACHOMETER AND BRAKE REGISTER:

__15___14___13___12___11___10____9____8____7____6____5____4____3____2____1____0__
|         |   TACH FEEDBACK CONTROL     |    |     BRAKE REGISTER               |
|         | J6 | J5 | J4 | J3 | J2 | J1 |    |HAND| J6 | J5 | J4 | J3 | J2 | J1 |
|_________|___________RW________________|____|_____________RW___________________|

The BRAKE REGISTER bits: a ONE turns off the brake on the corresponding joint
and enables the drive motor.  A ZERO sets the brake and disables the motor.

TACH FEEDBACK: a ONE enables direct tachometer feedback to the joint's drive
amplifier. This tach feedback is designed to provide high frequency
stabilization (10-200 HZ) of the arm's motion, a function which would overwork
the processor if done in the sampled data control loop. 
774004, ADC STATUS/CONTROL:

__15___14___13___12___11___10____9____8____7____6____5____4____3____2____1____0__
|         |  CHANNEL ADDRESS            |DONE|INT |    |    |ARM |PS  |PNIC|HOLD|
|         |                             |    |ENBL|    |    |RSET|GLCH|BUTN|    |
|_________|__________RW_________________|_R__|_RW_|____|____|_PW_|_R__|_R__|_RW_|

DONE comes on when the ADC has finished converting an input sample.  It is
cleared by writing into the CHANNEL ADDRESS byte or the FEEL bit.

INT ENBL, if on, makes the interface request a priority 7 interrupt through
location 134 when DONE comes on.

CHANNEL ADDRESS selects one of the input sample-and-hold circuits for conversion.
It does NOT sample the input from the sensor.  Writing into this byte makes the
ADC start converting.

HOLD: Writing a ONE into this bit makes all of the input follow-and-hold
circuits hold their values, and then begins a conversion of the selected
channel. This bit should be cleared after a group of channels has been
converted so that new values may be acquired.

ALARM STATUS BITS: Whenever an alarm condition happens, the brake register
is cleared (stopping the arm) and one of these bits comes on:

PNIC BUTN if somebody punched the red button on the brake switch box, or manually
disabled a brake with one of the switches.

PS GLTCH if the power supply failed or drooped more than 20% for about 100 ms.
Pulling on the yellow emergency cord along the perimeter of the hand-eye table
drops motor power, which also causes this alarm condition to occur. A program which
services the alarm interrupt can determine if the cord was pulled (or if something
serious has happened to the power supply) by determining whether or not this
alarm status bit can be reset by the ERROR RESET function in the DAC register,
or the ARM RESET function in the ADC register.
The alarm logic is enabled for interrupt at level 7 through location 200 after a
write reference to the DAC sample byte, and is disabled by ARM RESET.

A bit to indicate that the CPU timeout has occurred will be installed soon.

774006, ADC SAMPLE:

__15___14___13___12___11___10____9____8____7____6____5____4____3____2____1____0__
|                        |                                                      |
|         SIGN           | MSB                                              LSB |
|__________R_____________|____________R_________________________________________|

This register contains the digital equivalent of the analog value in the
selected sample-and-hold.  The format is as a signed (2's complement) integer
with 12 bits of precision.  The most positive value is 3777 (octal) and the
most negative is 174000.  Zero is the middle of the scale.
DAC AND ADC CHANNEL ASSIGNMENTS:

 ADC
CHANNEL		JOINT
NUMBER		SENSOR

0		FINGER CONTACT #1
1		FINGER CONTACT #2
2		JOINT 4 POT WIPER #1
3		JOINT 5 POT
4		JOINT 6 POT WIPER #1
5		HAND POT
6		JOINT 4 TACH
7		JOINT 5 TACH
10		JOINT 2 TACH
11		JOINT 3 TACH
12		JOINT 6 POT WIPER #2
13		JOINT 4 POT WIPER #2
14		JOINT 2 POT
15		JOINT 3 POT
16		UNUSED
17		UNUSED
20		JOINT 1 TACH
21		JOINT 1 POT
22-77		UNUSED


 DAC
CHANNEL		JOINT
NUMBER		FUNCTION

0		NULL CHANNEL (WHEN SELECTED, ZEROES ALL CHANNELS)
1		JOINT 1
2		JOINT 2
3		JOINT 3
4		JOINT 4
5		JOINT 5
6		JOINT 6
7		HAND
10-17		UNUSED

ARM INTERFACE PROGRAMMING NOTES

It is necessary to clear the alarm cnditions before the arm can be
run.  Therefore, the "ERROR RESET" bit must be set in the DAC word
before any attempt is made to release a brake or write DAC samples
into a DAC channel.  The ADC status register should be tested after
"ERROR RESET" is set, to make sure that both "PS GLITCH" and "PANIC
BUTTON" bits are off.  After the ERROR RESET bit is pulsed, the
program has roughly 100 milliseconde in which to begin writing into
the DAC sample register, and successive DAC samples must be
transferred at least once every 100 ms for as long as it is desired
to continue running the arm. 

When an error of any kind occurs, the drivers are all disabled, all
of the sample-and-hold amplifiers are held at zero volts output, and
the brake/tach register is cleared (setting all the brakes and
disabling all tach feedback).

Pulling on the yellow cord around the table drops motor power, but
doesn't affect brake power.  The red "MOTOR POWER ON" button must be
pressed to re-enable motor power.  Power may be removed from the
entire hand/eye table by hitting the "STOP" button in the box on the
side of the table beneath the COHU camera. Since the UNIBUS no longer
terminates in the arm interface, turning the power off with the
"STOP" button no longer inhibits the PDP-11 from accessing memory or
any peripherals other than the arm.

It is recommended that the ADC and DAC be serviced at their maximum
interrupt rate once every 1/60th of a second. 

If any DAC channels are being used, all must be refreshed.